Temperature and voltage droop-aware test scheduling during scan shift operation

Process-Variation and Temperature Aware SoC Test Scheduling Technique

High temperature and process variation are undesirable phenomena affecting modern Systems-on-Chip (SoC). High temperature is a well-known issue, in particular during test, and should be taken care of in the test process. Modern SoCs are affected by large process variation and therefore experience large and time-variant temperature deviations. A traditional test schedule which ignores these devi...

Switching Activity Reduction Using Scan Shift Operation

This paper presents BIST TPG (built in self test) for low power dissipation and high fault coverage a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG subside transitions...

Process-voltage-temperature Aware Nanoscale Circuit Optimization

On Multiprocessor Temperature-Aware Scheduling Problems

We study temperature-aware scheduling problems under the model introduced by Chrobak et al. in [6]. We consider a set of parallel identical processors and three optimization criteria: makespan, maximum temperature and (weighted) average temperature. On the positive side, we present polynomial time approximation algorithms for the minimization of the makespan and the maximum temperature, as well...

Temperature Aware and Defect-Probability Driven Test Scheduling for System-on-Chip

The high complexity of modern electronic systems has resulted in a substantial increase in the time-to-market as well as in the cost of design, production, and testing. Recently, in order to reduce the design cost, many electronic systems have employed a core-based system-onchip (SoC) implementation technique, which integrates pre-defined and pre-verified intellectual property cores into a sing...